1. Field of the Invention
The present invention relates to a semiconductor protection element, a semiconductor device and a method for manufacturing the same, and more particularly to the semiconductor protection element and the semiconductor device in which an electrostatic protection circuit to protect the semiconductor protection element or the semiconductor device from electrostatic discharge (ESD) is formed therein and the method for manufacturing the same.
The present application claims priority of Japanese Patent Application No. 2003-066161 filed on Mar. 12, 2003, which is hereby incorporated by reference.
2. Description of the Related Art
In recent years, in order to serve the need for scaling down a semiconductor protection element, it is necessary that an impurity diffusion layer making up a source region and a drain region have to be formed so that the impurity diffusion layer has a shallow depth.
However, formation of the impurity diffusion layer having a shallow depth causes resistance values in the source region and drain region to become high and the current driving capability of a transistor to be deteriorated remarkably.
To solve such the problem, a transistor is proposed which has a structure in which a silicide layer is selectively formed in a source region and a drain region to lower a resistance value on the source region and drain region. Such the structure is generally called as a salicide structure.
However, the salicide has a problem in that, though it is possible to lower a resistance value in the source region and in the drain region, it is vulnerable to electrostatic discharge (ESD).
In general, in order for an integrated circuit to be able to be resistant to electrostatic discharge (ESD), the following two conditions have to be satisfied.
(1) A protecting element mounted on an integrated circuit efficiently removes electrostatic discharge (ESD) so that an overvoltage and an overcurrent caused by the electrostatic discharge (ESD) both are not applied to object elements to be protected.
(2) A protecting element itself mounted on an integrated circuit is resistant to electrostatic discharge (ESD).
In the integrated circuit having the salicide structure, the above condition (2) becomes a big problem. The resistance of the protecting element to electrostatic discharge (ESD) is determined depending on distribution of resistance values from a drain to a source. If there exists a local region in which a resistance value is large compared with other region, heat is locally generated in the region, which causes high probability of occurrence of an electrostatic breakdown.
In a transistor having the salicide structure, as described above, since a resistance value is extremely lowered by introducing silicide in the source region and the drain region, heat is locally generated in a region from an LDD (Lightly-doped Drain)-structured region to a channel region formed at both ends of a gate of the transistor and, as a result, the resistance to electrostatic discharge (ESD) is remarkably lowered compared with a transistor having no salicide structure.
To solve these problems, various types of semiconductor devices are proposed.
FIG. 26 shows a first conventional example of a semiconductor device 200 disclosed in Japanese Patent No. 2773220 which corresponds to Japanese Patent Application Laid-open No. 02-271673. 
The semiconductor device 200 includes a P-type substrate 201 on which an N+ diffusion layer 202 and an LDD-structured layer 203 of impurity concentration being lower than that in the N+ diffusion layer 202 in a manner that the two layers overlap each other are formed.
On the N+ diffusion layer 202 are formed, in a selective manner, a first silicide layer 204a, a second silicide layer 204b, and a third silicide layer 204c. On the first silicide layer 204a is formed a source electrode 205 and on the third silicide layer 204c is formed a drain electrode 206.
On the P-type substrate 201 between the first silicide layer 204a and the second silicide layer 204b is formed a gate insulating film 207, in a lower position of which, however, the LDD-structured layer 203 is not formed, and on the gate insulating film 207 is formed a gate electrode 208. A side wall 209 is formed in a manner that it surrounds the gate electrode 208. FIG. 27 is a cross-sectional view of a semiconductor device 210, shown as a second conventional example, disclosed in U.S. Pat. No. 6,479,870.
The semiconductor device 210 shown in FIG. 27 differs from that shown in FIG. 26 in that an N-type well 211 is formed on a surface of a P-type substrate 201 between a second silicide layer 204b and a third silicide layer 204c and in that a field oxide film 212, instead of an LDD-structured layer 203 and an N+ diffusion layer 202, is formed between the second silicide layer 204 and the third silicide layer 204c. 
FIG. 28 is a cross-sectional view of a semiconductor device 220, shown as a third conventional example, disclosed in U.S. Pat. No. 5,637,902.
The semiconductor device 220 shown in FIG. 27 differs from that shown in FIG. 26 in that an N-type well 221 is formed on a surface of a P-type substrate 201 between a second silicide layer 204b and a third silicide layer 204c and in that a gate electrode structure 222 made up of a gate oxide film, gate electrode, and a side wall, instead of an LDD-structured layer 203 and N+ diffusion layer 202, is formed the second silicide layer 204b and the third silicide layer 204c. 
The semiconductor devices 200, 210, and 220 shown, respectively, in FIGS. 26, 27, and 28 have regions 230a, 230b, and 230c in each of which a silicide layer is not formed, respectively, between the second silicide layer 204b and third silicide layer 204c. Thus, by having the regions 230a, 230b, and 230c with no silicide layer being formed, it is made possible to make uniform resistance existing between a wiring material (not shown) to an end of each of the source electrode and the drain electrode, which enables resistance to electrostatic discharge (ESD) to be increased.
In the semiconductor device 200 shown in FIG. 26, on the N+ diffusion layer 202 which serves as a region where an impurity of high concentration is implanted, is formed the region 230d in which the silicide layers 204b and 204c are not formed and the silicide layer 204b and 204c serve as a region having a low resistance value and the region 230a serves as a region having an intermediate resistance value.
In the semiconductor device 210 shown in FIG. 26 and in the semiconductor device 220 shown in FIG. 28, the regions such as the N-type wells 211 and 221, or the LDD-structured layer 203 in which the impurity of low concentration is implanted function as regions having a high resistance value.
However, in the semiconductor device 200 shown in FIG. 26, since the N+ diffusion layer 202 into which the impurity of high concentration has been implanted exists directly below the region 230a in which no silicide layer has been formed, a resistance value per a unit area in the semiconductor device 200 is small. Therefore, if a resistor element is made up of only regions having small resistance values as in the case of the semiconductor device 200, in order to acquire a desired resistance value, the resistor element, that is, an area of the region 230a has to be made large in a manner to correspond to the desired resistance value, which makes it impossible to manufacture a semiconductor device having a small area and, as a result, makes it difficult to meet the recent years' need for scaling down semiconductor devices.
In this respect, if the resistor element is made up of regions having high resistance as in the case of the semiconductor device 210 shown in FIG. 27 and the semiconductor device 220 shown in FIG. 28, unlike in the case of the semiconductor device 220 shown in FIG. 28, it is made possible to reduce the area of the semiconductor device. However, if a big current caused by application of electrostatic discharge (ESD) happens to flow, there is a problem in that the resistor element itself is easily broken down.
This problem is described by referring to FIG. 29 below. FIG. 29A is a cross-sectional view showing the field oxide film 212 and regions surrounding the field oxide film 212 making up the semiconductor device 210 shown in FIG. 27. FIG. 29B is a graph showing a relation between a position corresponding to the region shown in FIG. 29A and a voltage to be applied.
As is apparent from FIG. 29B, if a big current flows due to application of electrostatic discharge (ESD), a rapid voltage drop from V1 to V2 occurs in the region 230b having a high resistance value. As a result, heat is locally generated in the region 230b having a high resistance value in a concentrated manner. Especially, in order to reduce an area of a semiconductor device, the region 230b having high resistance values is formed so as to have a small area and, therefore, an amount of heat generated per unit area becomes very large. Therefore, a probability that the resistor element itself is thermally broken down becomes very large.